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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Analog Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally-controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. * * * * * * * * * Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage Range = 3.0 Vdc to 18 Vdc Analog Voltage Range (VDD - VEE) = 3.0 to 18 V Note: VEE must be VSS Linearized Transfer Characteristics Low-noise - 12 nV/Cycle, f 1.0 kHz Typical Pin-for-Pin Replacement for CD4051, CD4052, and CD4053 For 4PDT Switch, See MC14551B For Lower RON, Use the HC4051, HC4052, or HC4053 High-Speed CMOS Devices
MC14051B MC14052B MC14053B
L SUFFIX CERAMIC CASE 620
v
P SUFFIX PLASTIC CASE 648
D SUFFIX SOIC CASE 751B
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MAXIMUM RATINGS*
Symbol VDD Parameter Value Unit V DC Supply Voltage (Referenced to VEE, VSS VEE) - 0.5 to + 18.0 Vin, Vout Iin Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Inputs and VEE for Switch I/O) Input Current (DC or Transient), per Control Pin Switch Through Current Storage Temperature - 0.5 to VDD + 0.5 10 25 500 V mA mA Isw PD Power Dissipation. per Package mW Tstg - 65 to + 150
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = - 55 to 125C for all packages.
_C
TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating:"P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
MC14051B 8-Channel Analog Multiplexer/Demultiplexer
6 11 10 9 13 14 15 12 1 5 2 4 INHIBIT A B C X0 X1 X 3 X2 COMMON X3 OUT/IN X4 X5 X6 X7 VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
MC14052B Dual 4-Channel Analog Multiplexer/Demultiplexer
CONTROLS 6 10 9 12 14 15 11 1 5 2 4 INHIBIT A X B X0 X1 X2 X3 Y0 Y Y1 Y2 Y3
MC14053B Triple 2-Channel Analog Multiplexer/Demultiplexer
6 11 10 9 12 13 2 1 5 3 INHIBIT X A B C X0 Y X1 Y0 Y1 Z Z0 Z1 14
CONTROLS
13 COMMONS OUT/IN 3
CONTROLS
15
COMMONS OUT/IN
SWITCHES IN/OUT
SWITCHES IN/OUT
SWITCHES IN/OUT
4
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
VDD = PIN 16 VSS = PIN 8 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be VSS.
REV 3 1/94
(c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995
MC14051B MC14052B MC14053B 1
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SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to VEE) SUPPLY REQUIREMENTS (Voltages Referenced to VEE) CONTROL INPUTS -- INHIBIT, A, B, C (Voltages Referenced to VSS)
#Data labeled "Typ" is not to be used for design purposes, but is intended as an indication of the IC's potential performance. * For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.)
ELECTRICAL CHARACTERISTICS
Capacitance, Feedthrough (Channel Off)
Capacitance, Common O/I
Capacitance, Switch I/O
Off-Channel Leakage Current (Figure 10)
ON Resistance Between Any Two Channels in the Same Package
ON Resistance
Output Offset Voltage
Recommended Static or Dynamic Voltage Across the Switch** (Figure 5)
Recommended Peak-to-Peak Voltage Into or Out of the Switch
Input Capacitance
Input Leakage Current
High-Level Input Voltage
Low-Level Input Voltage
Total Supply Current (Dynamic Plus Quiescent, Per Package
Quiescent Current Per Package
Power Supply Voltage Range
MC14051B MC14052B MC14053B 2
Characteristic Vswitch Symbol ID(AV) Ron VOO VDD CI/O CO/I CI/O VI/O Ron IDD VIH Cin VIL Ioff Iin VDD 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 -- -- -- -- -- -- -- -- -- VDD - 3.0 VSS VEE Pins Not Adjacent Pins Adjacent Inhibit = VDD (MC14051B) (MC14052B) (MC14053B) Inhibit = VDD Vin = VIL or VIH (Control) Channel to Channel or Any One Channel Vswitch 500 mV**, Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) Vin = 0 V, No Load Channel On Channel On or Off Vin = 0 or VDD Ron = per spec, Ioff = per spec Ron = per spec, Ioff = per spec TA = 25_C only (The channel component, (Vin - Vout)/Ron, is not included.) Control Inputs: Vin = VSS or VDD, Switch I/O: VEE VI/O VDD, and Vswitch 500 mV**
v
Test Conditions
v
v
v
Min
3.5 7.0 11
3.0
-- --
-- -- --
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
- 55_C
Typical
100
0.1
VDD
Max
800 400 220
600
1.5 3.0 4.0
5.0 10 20
70 50 45
18
-- --
-- -- --
--
--
--
-- -- --
Min
3.5 7.0 11
3.0
-- --
-- -- --
--
--
-- -- --
-- -- --
--
--
--
-- -- --
-- -- --
0
0
(0.07 A/kHz) f + IDD (0.20 A/kHz) f + IDD (0.36 A/kHz) f + IDD
0.00001
0.05
MOTOROLA CMOS LOGIC DATA
Typ # 0.005 0.010 0.015 25_C 0.15 0.47 2.75 5.50 8.25 2.25 4.50 6.75 250 120 80 5.0 60 32 17 10 25 10 10 10 -- -- -- 100 1050 500 280 0.1 VDD Max 600 7.5 1.5 3.0 4.0 5.0 10 20 70 50 45 18 -- -- -- -- -- -- -- -- -- -- Min 3.5 7.0 11 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 125_C 1000 1200 520 300 VDD Max 135 95 65 300 150 300 600 1.0 1.5 3.0 4.0 18 -- -- -- -- -- -- -- -- -- -- -- VPP Unit mV V A A A nA pF pF pF pF V V V
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* The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not lo be used for design purposes but In intended as an indication of the IC's potential performance.
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE
Crosstalk, Control Input to Common O/I (Figure 9) (R1 = 1 k, RL = 10 k Control tTLH = tTHL = 20 ns, Inhibit = VSS)
Channel Separation (Figure 8) (RL = 1 k, Vin = 1/2 (VDD-VEE) p-p, fin = 3.0 MHz
Second Harmonic Distortion (RL = 10K, f = 1 kHz) Vin = 5 VPP Bandwidth (Figure 7) (RL = 1 k, Vin = 1/2 (VDD-VEE) p-p, CL = 50pF 20 Log (Vout/Vin) = - 3 dB) Off Channel Feedthrough Attenuation (Figure 7) RL = 1K, Vin = 1/2 (VDD - VEE) p-p fin = 4.5 MHz -- MC14051B fin = 30 MHz -- MC14052B fin = 55 MHz -- MC14053B
Propagation Delay Times (Figure 6) Switch Input to Switch Output (RL = 10 k) MC14051 tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 11 ns tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns MC14052 tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns
MOTOROLA CMOS LOGIC DATA
Control Input to Output (RL = 10 k, VEE = VSS) MC14051B Inhibit to Output (RL = 10 k, VEE = VSS) Output "1" or "0" to High Impedance, or High Impedance to "1" or "0" Level MC14051B MC14053B MC14052B MC14053B MC14052B MC14053 tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns Characteristic tPHZ, tPLZ, tPZH, tPZL tPLH, tPHL tPLH, tPHL Symbol BW -- -- -- -- VDD - VEE Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 10 10 10 10 10
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs must be left open.
v VSS unless otherwise indicated)
MC14051B MC14052B MC14053B 3
Typ # All Types - 50 - 50 0.07 300 120 80 325 130 90 360 160 120 275 140 110 300 155 125 350 170 140 25 8.0 6.0 75 17 30 12 10 35 15 12 Max 600 240 160 650 260 180 720 320 240 550 280 220 600 310 250 700 340 280 65 20 15 75 30 25 90 40 30 -- -- -- -- -- MHz Unit mV dB dB ns ns ns ns ns ns ns ns ns %
VDD IN/OUT
VDD V DD OUT/IN
VEE
VDD LEVEL CONVERTED CONTROL
IN/OUT
OUT/IN
VEE
CONTROL
Figure 1. Switch Circuit Schematic
TRUTH TABLE
Control Inputs Select Inhibit 0 0 0 0 0 0 0 0 1 C* 0 0 0 0 1 1 1 1 x B 0 0 1 1 0 0 1 1 x A 0 1 0 1 0 1 0 1 x MC14051B X0 X1 X2 X3 X4 X5 X6 X7 None None ON Switches MC14052B Y0 Y1 Y2 Y3 X0 X1 X2 X3 MC14053B Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None X0 X1 X0 X1 X0 X1 X0 X1 INH A B C 6 11 10 9 8 X0 13 X1 14 X2 15 X3 12 X4 1 X5 5 X6 2 X7 4
16
VDD BINARY TO 1-OF-8 DECODER WITH INHIBIT VEE
LEVEL CONVERTER
VSS
7
3X
* Not applicable for MC14052 x = Don't Care
Figure 2. MC14051B Functional Diagram
16 INH 6 A 10 B9 8 X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 VSS 7 LEVEL CONVERTER
VDD 16 BINARY TO 1-OF-4 DECODER WITH INHIBIT VEE
13 X
VDD BINARY TO 1-OF-2 DECODER WITH INHIBIT VEE
14 X
INH A B C
6 11 10 9 8
LEVEL CONVERTER VSS 7
X0 12 X1 13 Y0 2
3Y
Y1 1 Z0 5 Z1 3
15 Y
4Z
Figure 3. MC14052B Functional Diagram
Figure 4. MC14053B Functional Diagram
MC14051B MC14052B MC14053B 4
MOTOROLA CMOS LOGIC DATA
TEST CIRCUITS
ON SWITCH CONTROL SECTION OF IC V SOURCE VDD VEE VEE VDD PULSE GENERATOR LOAD INH RL CL A B C
Vout
Figure 5. V Across Switch
Figure 6. Propagation Delay Times, Control and Inhibit to Output
A, B, and C inputs used to turn ON or OFF the switch under test. A B C VSS INH RL Vin VDD - VEE 2 RL Vout CL = 50 pF INH A B C ON
OFF Vout RL CL = 50 pF
VDD - VEE 2
Vin
Figure 7. Bandwidth and Off-Channel Feedthrough Attenuation
Figure 8. Channel Separation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST VDD VEE OTHER CHANNEL(S) VEE VDD VEE VDD
A B C INH R1 RL
Vout CL = 50 pF
CONTROL SECTION OF IC
COMMON
Figure 9. Crosstalk, Control Input to Common O/I
NOTE: See also Figures 7 and 8 on Page 6-51.
Figure 10. Off Channel Leakage
MOTOROLA CMOS LOGIC DATA
MC14051B MC14052B MC14053B 5
VDD
KEITHLEY 160 DIGITAL MULTIMETER
10 k VDD VEE = VSS 1 k RANGE X-Y PLOTTER
Figure 11. Channel Resistance (RON) Test Circuit TYPICAL RESISTANCE CHARACTERISTICS
350 R ON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 350 300 250 200 150 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 TA = 125C 25C - 55C
TA = 125C 25C - 55C
8.0
10
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = - 7.5 V
700 RON , "ON" RESISTANCE (OHMS) R ON , "ON" RESISTANCE (OHMS) 600 500 400 300 TA = 125C 200 25C 100 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 - 55C 4.0 6.0 8.0 10 350 300 250 200 150
Figure 13. VDD = 5.0 V, VEE = - 5.0 V
TA = 25C
VDD = 2.5 V
5.0 V 100 50 0 - 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10 7.5 V
Vin, INPUT VOLTAGE (VOLTS)
Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = - 2.5 V PIN ASSIGMENT MC14051B
X4 X6 X X7 X5 INH VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD X2 X1 X0 X3 A B C Y0 Y2 Y Y3 Y1 INH VEE VSS
Figure 15. Comparison at 25C, VDD = - VEE
MC14052B
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD X2 X1 X X0 X3 A B Y1 Y0 Z1 Z Z0 INH VEE VSS
MC14053B
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Y X X1 X0 A B C
MC14051B MC14052B MC14053B 6
MOTOROLA CMOS LOGIC DATA
APPLICATIONS INFORMATION
Figure A illustrates use of the on-chip level converter detailed in Figures 2, 3, and 4. The 0-to-5 V Digital Control signal is used to directly control a 9 Vp-p analog signal. The digital control logic levels are determined by VDD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD - VSS = 5 V maximum swing above V SS ; V SS - V EE = 5 V maximum swing below VSS. The example shows a 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients
+5 V VDD VSS VEE + 4.5 V 9 Vp-p ANALOG SIGNAL +5 V SWITCH I/O MC14051B MC14052B MC14053B 0-TO-5 V DIGITAL CONTROL SIGNALS INHIBIT, A, B, C
above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE. For example, V DD = + 10 V, V SS = + 5 V, and V EE - 3 V is acceptable. See the Table below.
-5 V
COMMON O/I
9 Vp-p ANALOG SIGNAL
GND
- 4.5 V
EXTERNAL CMOS DIGITAL CIRCUITRY
Figure A. Application Example
VDD DX ANALOG I/O DX VEE VEE COMMON O/I DX VDD DX
MOTOROLA CMOS LOGIC DATA
IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII
Figure B. External Germanium or Schottky Clipping Diodes POSSIBLE SUPPLY CONNECTIONS
VDD In Volts +8 +5 +5 +5 VSS In Volts 0 0 0 0 VEE In Volts -8 Control Inputs Logic High/Logic Low In Volts + 8/0 + 5/0 + 5/0 + 5/0 Maximum Analog Signal Range In Volts + 8 to - 8 = 16 Vp-p - 12 0 + 5 to - 12 = 17 Vp-p + 5 to 0 = 5 Vp-p -5 -5 + 5 to - 5 = 10 Vp-p + 10 +5 + 10/ + 5 + 10 to - 5 = 15 Vp-p
MC14051B MC14052B MC14053B 7
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-B-
1 8
C
L
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
MC14051B MC14052B MC14053B 8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA CMOS LOGIC DATA
*MC14051B/D*
MC14051B MC14052B MC14053B MC14051B/D 9

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